1. Field of the Invention
The invention relates generally to the field of fabricating integrated circuit devices. More particularly, the invention relates to methods of pretreating semiconductor wafers and/or selectively forming hemispherical grain silicon (HSG).
2. Discussion of the Related Art
As integrated circuit device dimensions continue to shrink, new processing methods are developed to facilitate fabrication of smaller device features. The basic driving forces motivating the reduction in device geometry are production cost and device performance. A new processing solution is expected to replace an existing process while simultaneously permitting cheaper and/or simpler production methods.
Dynamic random access memory (DRAM) manufacturers are interested in shrinking the capacitor size of each memory cell, while maintaining the same charge per cell. Retaining the same charge per cell while simultaneously shrinking the size of the capacitor requires an increase in the charge per unit area that the capacitor can hold. The charge per unit area of the capacitor can be increased by increasing the dielectric constant of the dielectric layer between the cell capacitor plates and/or increasing the surface area of the capacitor plates.
Prior art approaches to increasing the surface area of the capacitor plates include the use of a process called hemispherical grain silicon (HSG). HSG is described in detail in U.S. Pat. Nos. 5,385,863; 5,407,534; 5,634,974; 5,656,531; and 5,629,223, the entire contents of all of which are hereby expressly incorporated by reference into the present application as if fully set forth herein.
HSG is a process in which an amorphous silicon layer is heated to a temperature slightly below the one at which bulk crystallization occurs. At this intermediate temperature range, silicon atoms migrate along the surface and form clusters which are between 200 and 1200 angstroms in diameter. The silicon clusters are hemispherically shaped. A DRAM cell capacitor plate coated with HSG has more surface area per unit cell area compared to a cell of the same dimensions which is not coated by HSG. The ratio defined by the surface area per unit cell area of an HSG surface divided by that of a corresponding non-HSG surface is called the area enhancement factor (AEF). AEF values of 1.5-3.5 can be achieved using the HSG method.
Various methods of depositing HSG have been described. These methods include low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), molecular beam epitaxy (MBE), and rapid thermal chemical vapor deposition (RTCVD). In order to form HSG on 3-dimensional structures, the HSG process must be performed selectively so that the hemispherical grains of silicon are formed only on the existing capacitor cell areas and not on the surrounding dielectric material. Selective deposition requires a contaminant-free amorphous silicon surface. Selective deposition also requires that the time the substrate is exposed to deposition gasses be substantially less than the time required for stable silicon nuclei to form on the dielectric layer.
The most widely used HSG formation processes include a seeding step in which the amorphous silicon substrate is exposed to a Si-containing source. During the seeding step, nucleation sites are formed at which the hemispherical grains of silicon grow. The seeding step is followed by an annealing step in which the substrate is heated. During the heating, silicon atoms migrate to the nucleation sites and HSG is formed.
However, a problem with this HSG technology is that it is difficult to maintain selectivity. Selectivity means that the HSG is deposited preferentially on some surfaces while it is substantially not deposited on other surfaces. In the prior art, the issue of selectivity is addressed by keeping the chemical reactor in which the HSG process is performed at a very low pressure or by adding fluorine-containing gasses during the deposition.
A significant disadvantage of keeping the reactor at a very low pressure is that the HSG process becomes highly pressure dependent. The very low pressure can cause severe fluctuations in quality and selectivity, depending on the amount of time during which the chamber has been exposed to vacuum.
A significant disadvantage of adding fluorine-containing gasses during the deposition is that fluorine is not a desirable substance on the surface of the amorphous silicon. The fluorine can interfere with both the migration of silicon atoms on the surface of the amorphous silicon and the HSG formation. Silicon atoms should be free to diffuse across the surface (migrate). Another disadvantage of using fluorine-containing gases during the deposition is that the fluorine can enhance dopant depletion in boron-doped electrodes. Therefore, what is needed is an approach to HSG that has better selectivity.
Another problem with this HSG technology is that quality and selectivity is degraded due to out-gassing of moisture from the underlying dielectric material during the HSG process. One approach to addressing this moisture out-gassing problem is to pump out the chamber for a longer period of time before commencing the HSG process. However, this approach has the significant disadvantage of increasing the total amount of time required to complete the overall HSG process, thereby reducing efficiency. A process chamber can only accommodate a given number of wafers at one time and the longer each process cycle takes, the fewer wafers can be processed per unit of time. Therefore, what is also needed is an approach to selectively forming HSG that has better efficiency.
Heretofore, the requirements of good selectivity, less process pressure dependence, unimpeded silicon migration, avoidance of dopant depletion, and efficiency referred to above have not been fully met. What is required is a solution that simultaneously addresses all of these requirements.